An important goal for the semiconductor industry is decreasing the size of semiconductor devices while increasing semiconductor performance. Planar transistors, such as metal oxide semiconductor field effect transistors (MOSFETs), are well suited for use in high-density integrated circuits (ICs).
Higher speed MOSFETs can be formed using strained device technology. One manufacturing method involves epitaxial growth of silicon on top of a relaxed silicon-germanium under layer. Tensile strain is induced in the silicon as the lattice of the silicon layer is stretched to mimic the larger lattice constant of the underlying silicon-germanium. Conversely, compressive strain could be induced by using a solid solution with a smaller lattice constant, such as silicon-carbon. Another closely related method involves replacing the source/drain region of a MOSFET with silicon-germanium.
One method of strained device technology is to deposit a layer of silicon-germanium (SiGe) on a bulk silicon wafer. The crystalline structure of SiGe is diamond, which is the same as silicon. However, the lattice constant in the SiGe is greater than that in Si. Therefore, when a thin silicon layer (thinner than critical thickness) is deposited on top of the SiGe layer the silicon crystal lattice may strain to align the silicon atoms with the atoms in the SiGe layer. Electrons in strained silicon experience less resistance and flow faster than in unstrained silicon, thus, increasing transistor performance.
Further methods of building high speed MOSFETs include Ge MOSFETs. Ge MOSFETs have a high intrinsic carrier mobility, which improves device speed. However, dopant activation in source/drain regions may be an issue in current Ge MOSFETs, especially the N-type MOSFET or N-FET. The external resistance of the Ge N-FET transistor may be greater than the external resistance of a conventional N-FET transistor. External resistance comprises the sum of the resistances associated with the ohmic contacts (metal to semiconductor and semiconductor to metal), the resistances within the source/drain region itself, the resistances of the region between the channel region and the source/drain regions (i.e. the source/drain extensions), and the interface resistances due to impurity (carbon, nitrogen, oxygen) contamination at the location of the initial substrate-epi-layer interface. The external resistance may reduce transistor performance.
For instance, the drive current of the N-FET may be impacted negatively if the external resistance of the N-FET is high. Drive current is the drain current of a MOS transistor with gate and drain connected to the supply voltage, and source and bulk grounded. Drive current is a significant device performance parameter.
Further, a desired low value for drain induced barrier lowering (DIBL) may not be achieved in high external resistance N-FET structures. DIBL is the measure of a transistor in the weak inversion regime. A potential barrier between the source and the channel region exists. The height of this barrier is a result of the balance between drift and diffusion current between the source and the channel region. If a high drain voltage is applied, the barrier height can decrease leading to an increased drain current. Thus, the drain current is controlled not only by the gate voltage, but also by the drain voltage. This parasitic effect can be accounted for by a threshold voltage reduction depending on the drain voltage.
Thus, there are challenges due to scaling planar bulk CMOS because of the high channel doping required to reduce the parasitic series source/drain resistance (Rsd) to acceptable values while employing shallow source/drain junction depth. What is needed then is a shallow, highly doped source/drain with reduced Rsd that provides a beneficial transistor strain.